1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device comprising a circuit operating in response to two clock signals having amplitudes of different voltage levels The present invention has particular applicability for a semiconductor integrated circuit device, for example, such as a gate array in which the number of terminals for externally receiving control signals is restricted.
2. Description of the Background Art
Generally, the number of I/O pins or terminals of an IC package housing a semiconductor integrated circuit (hereinafter referred to as an IC), for example such as a gate array is determined by a standard, corresponding to the size of the IC package. More specifically, for example, an IC package having 64 pins is standardized and an IC package having 80 pins is provided as an IC package having more pins than the number of 64. Therefore, for example, when 65 pins are required by an IC housed in a package, an IC package having 80 pins has to be used. As a result, the size of the IC package to be used becomes big, which is not preferable. Particularly, it is not preferable that the size of an IC package becomes big in order to provide a pin for inputting a control signal which is necessary only when the IC is tested.
FIG. 1 is a circuit diagram showing an example of an IC having a conventional selector circuit for testing. This selector circuit is found, for example, on page 16 in a CMOS standard cell design manual (MN72000 series) of Matsushita Electronics Corporation in 1986.
Referring to FIG. 1, the IC comprises two 8-bit ripple counters 1 and 2 for constituting a dividing circuit, a selector circuit 3 connected between the ripple counters 1 and 2 and an inner circuit 7 connected to receive output signals from the ripple counters 1 and 2. The ripple counter 1 is connected such that a toggle input T may receive a clock signal .phi.3 from the outside through a buffer 11 and also connected such that a reset input R may receive a reset signal RST from the outside through a buffer 12. The selector circuit 3 has one input connected to the output of the ripple counter 1 and the other input connected to receive the clock signal .phi.3 through the buffer 11. The ripple counter 2 has the toggle input connected to the output of the selector circuit 3 and the reset input R connected to receive the reset signal RST through the buffer 12. The inner circuit 7 is connected to receive the output signals of the ripple counter 1 and 2. The inner circuit 7 performs predetermined digital signal processing in response to the output signals from the counters 1 and 2. The output signals of the counters 1 and 2 are outputted to the outside through the buffers 13 and 14, respectively. The selector circuit 3 is connected to receive a test mode signal TM from the outside through a buffer 5. The selector circuit 3 comprises two AND gates 31 and 32, an OR gate 34 and an inverter 33.
In operation in the common mode, the test mode signal TM at a low level is externally applied to the selector circuit through the buffer 5. The selector circuit 3 connects an output Q of the ripple counter 1 to the toggle input T of the counter 2 in response to the signal T. As a result, a 16-bit counter is constituted by the counters 1 and 2. The inner circuit 7 performs a predetermined operation in response to the output signals from these two counters 1 and 2.
On the other hand, in operation in the test mode, the test mode TM at a high level is applied to the selector circuit 3. The selector circuit 3 is connected to the toggle input T of the ripple counter 2 to receive the clock signal .phi.3 in response to the signal TM. As a result, the clock signal .phi.3 is applied to the toggle input of each of the ripple counters 1 and 2 from the outside. Normal operation of the ripple counters 1 and 2 are recognized by confirming that the output levels of the counters 1 and 2 change every 128th clock of the clock signal .phi.3.
The select circuit 3 is provided for shortening time required for confirming the operation of the counters 1 and 2. More specifically, if the selector circuit 3 is omitted, it means that the output Q of the counter 1 is directly connected to the toggle input T of the counter 2. In this case, when a test for confirming the operation of the two counters 1 and 2 is performed, the clock signal .phi.3 of 32,768, (=2.sup.8 .times.2.sup.7) clocks is required, which requires a long testing time.
Although the selector circuit 3 is provided for shortening the testing time, a terminal for externally receiving the signal TM to control the circuit 3 is required. However, it is not preferable to provide a pin or a terminal only for the operation in the test mode as described above and there is a problem in which a big IC package has to be used to provide a terminal for receiving the signal TM.